1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor structure, and more particularly to a method of manufacturing an opening and a via opening.
2. Description of Related Art
With the rapid progress in integrated circuit (IC) technologies, device miniaturization and device integration are definitely on the rise and have become an important subject in various industries. Due to increasing integrity of ICs, the surface of a chip can hardly provide sufficient area for fabricating required interconnects. In order to comply with the high demand for the interconnects as the size of the semiconductor device is decreased, it is necessary to adopt two- or multi-level interconnects in current IC devices.
In most cases, dielectric layers are used to separate conductive layers (e.g. electrodes and conductive lines, or the conductive lines in different layers from one another). Thereby, the occurrence of short circuit resulting from direct contacts between each of the conductive layers can be avoided. Moreover, contact plugs or via plugs are formed in the dielectric layers to connect the upper conductive layer and the lower conductive layer.
However, with the decrease in line widths within the semiconductor devices and the increase in integrity, overlay errors among film layers or the limitation of the optical design rule to a lithography and etching process may frequently occur, which leads to misalignment or an un-landed phenomenon when the dielectric layers are defined to form the opening.
Please refer to FIG. 1 which is a cross-sectional view depicting a structure of a conventional via opening. An aluminum conductive line 110 and a titanium nitride layer 120 are disposed on a substrate 100, and a dielectric layer 130 covers the titanium nitride layer 120 and the substrate 100. On account of the un-landed phenomenon, a via opening 145 is not fully formed on the titanium nitride layer 120 during the process of etching the via opening 145. Instead, a divot 155 is formed at a sidewall of the aluminum conductive line 110 by etching through the dielectric layer 130 and the titanium nitride layer 120, such that the aluminum conductive line 110 below the titanium nitride layer 120 is exposed. Thus, impurities and residues e.g. fluorine aluminum (AlF3) generated by the etching process cannot be completely removed in a following cleaning process. Thereby, the film layer subsequently deposited in the via opening 145 is further affected, which leads to variations in contact resistance of the via plugs and to reduction of the electrical quality of the device. The influence caused by said residues is particularly significant in a deep sub-micron fabrication process.